module rrarb_Nto1    (
       clk           ,
       rst_n         ,
       req           ,
       grant         ,
       switch_to_next
);

   parameter REQ_CNT = 4;
   parameter LATCH_GNT = 0; // latch grant till switch_to_next

   input                clk           ;
   input                rst_n         ;
   input  [REQ_CNT-1:0] req           ;
   output [REQ_CNT-1:0] grant         ;
   input                switch_to_next;

   wire [REQ_CNT-1:0] grant_c         ;
   reg  [REQ_CNT-1:0] grant_r         ;

   generate
     if(LATCH_GNT) begin: need_latch
       rrarb_Nto1_raw #(.REQ_CNT(REQ_CNT)) x_arb (
         .clk            ( clk                  ) ,
         .rst_n          ( rst_n                ) ,
         .req            ( req[REQ_CNT-1:0]     ) ,
         .grant          ( grant_c[REQ_CNT-1:0] ) ,
         .switch_to_next ( switch_to_next       )
       );

       always @(posedge clk or negedge rst_n) begin
         if(~rst_n) begin
           grant_r[REQ_CNT-1:0] <= {REQ_CNT{1'b0}};
         end else if(switch_to_next) begin
           grant_r[REQ_CNT-1:0] <= {REQ_CNT{1'b0}};
         end else if(grant_r[REQ_CNT-1:0] == {REQ_CNT{1'b0}}) begin
           grant_r[REQ_CNT-1:0] <= grant_c[REQ_CNT-1:0];
         end
       end

       assign grant[REQ_CNT-1:0] = |grant_r[REQ_CNT-1:0] ? grant_r[REQ_CNT-1:0] : grant_c[REQ_CNT-1:0];
     end else begin: no_latch
       rrarb_Nto1_raw #(.REQ_CNT(REQ_CNT)) x_arb (
         .clk            ( clk                ) ,
         .rst_n          ( rst_n              ) ,
         .req            ( req[REQ_CNT-1:0]   ) ,
         .grant          ( grant[REQ_CNT-1:0] ) ,
         .switch_to_next ( switch_to_next     )
       );
     end
   endgenerate

endmodule
